1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to a method for forming a gate which provides a reduced corner recess in the adjacent shallow trench isolation.
2) Description of the Prior Art
Shallow trench isolations (STI) are widely used in semiconductors manufacturing to provide isolation of active areas on a substrate. However, STI's are susceptible to a problem known as the corner recess problem. Device processing requires wet and/or dry etch steps after the STI has undergone chemical mechanical polishing (CMP) to its final size. These etch steps inevitably etch away part of the STI causing corners of the STI to be recessed. Recessed corners can trap polysilicon and nitride residues during subsequent removal steps, such as gate etching and spacer etching. They can also cause junction leakage associated with salicide formation.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 4,635,347 (Lien et al.) shows a self-aligned TiS.sub.x, gate and contact forming process.
U.S. Pat. No. 5,731,241 (Jang et al.) discloses a O3-TEOS sacrificial layer over a STI.
U.S. Pat. No. 5,563,104 (Jang et al.) and U.S. Pat. No. 5,804,498 (Jang et al.) disclose O3-TEOS deposition processes with reduced sensitivity to the composition of underlying layers.
U.S. Pat. No. 5,605,853 (Yoo) shows a TiS.sub.x, process without a RPO layer.